The development of efuse technology is based on the melting characteristics of poly-silicon fuse. The initial resistance of an efuse may be small. When a high electrical current flows through the efuse, the efuse can be melted and the resistance of the efuse multiplies. The value of the data stored in the memory cell consisting of an efuse can thus be determined by whether the efuse has been melted.
As shown in FIG. 1, an existing efuse memory includes m word lines, n column selection transistors, n bit lines, n sense amplifiers, and an efuse memory array. M and n are positive integers.
The m word lines include a 1st word line (WL1), a 2nd word line (WL2), . . . , and an mth word line (WLm). The n column selection transistors include a 1st column selection transistor M1, a 2nd column selection transistor M2, a 3rd column selection transistor M3, . . . , and an nth column selection transistor Mn. The source of each of the n column selection transistors is connected to the power supply voltage VDD.
The n bit lines include a 1st bit line (BL1), a 2nd bit line (BL2), a 3rd bit line (BL3), . . . , and an nth bit line (BLn). Each bit line is connected to the drain of the corresponding column selection transistor. For example, the nth bit line (BLn) is connected to the nth column selection transistor.
The n sense amplifiers include a 1st sense amplifier (SA1), a 2nd sense amplifier (SA2), a 3rd sense amplifier (SA3), . . . , and an nth sense amplifier (SAn). Each sense amplifier is connected to the corresponding bit line. For example, the nth sense amplifier (SAn) is connected to the nth bit line (BLn).
The efuse memory array includes memory cells arranged in an m (row) by n (column) array. Each of the m word lines corresponds to one of the m rows of memory cells, and each of the n bit lines corresponds to one of the n columns of memory cells. That is, one word line and one bit line together correspond to one memory cell.
Each memory cell includes a row selection transistor and an efuse. The gate of the row selection transistor is connected to the word line corresponding to the memory cell. The drain of the row selection transistor is connected to a first end of the efuse. The source of the row selection transistor is connected to the ground voltage GND. A second end of the efuse is connected to the bit line corresponding to the memory cell.
For example, the memory cell 10 refers to the memory cell located at 1st row, 1st column), and the memory cell 10 corresponds to the 1st world line (WL1) and the 1st bit line (BL1). The memory cell 10 includes a row selection transistor M0 and an efuse F0. The gate of the row selection transistor M0 is connected to the 1st world line (WL1), and the drain of the row selection transistor M0 is connected to the first end of the efuse F0. The source of the row selection transistor M0 is connected to the ground voltage GND, and the second end of the efuse F0 is connected to the 1st bit line (BL1).
The ON/OFF state of a column selection transistor can be controlled by applying a suitable voltage on the gate of the column selection transistor. The ON/OFF state of a row selection transistor in a memory cell in a row of the memory array can be controlled by applying a suitable voltage on the corresponding word line. When the row selection transistor of a memory cell and the column selection transistor corresponding to the memory cell are both on, the efuse of the memory cell can be melted. The operation of melting an efuse of a memory cell can be known as a write operation to the memory cell. The value of the resistance of the efuse can be used to determine whether the efuse is melted. For example, when the value of the resistance is greater than a threshold value, the efuse is considered melted. When the value of the resistance is less than the threshold value, the efuse is considered not melted.
Once the efuse of a memory cell is melted, the memory cell may not be written again using the write operation. That is, the memory cell can be written only once during a programming process. Data “1” is often considered to be the data to be written into a memory cell. That is, to program the data “1” into a memory cell, the efuse of the memory cell to be written needs to be melted in order to store “1” into the memory cell. To program data “0” into a memory cell, the efuse of the memory cell for storing the data “0” needs not be melted.
However, programming failures may occur when programming memory cells. That is, the efuse may not be melted after a write operation to a memory cell, causing the data stored in the memory cell to be erroneous. Accordingly, a read operation to access the data stored may obtain the erroneous data. As a result, the production yield of the memory device may be reduced. The disclosed methods are directed to solve one or more problems set forth above.